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Micrel, Inc.
ULTRA-PRECISION 1:4 LVPECL FANOUT BUFFER/TRANSLATOR WITH INTERNAL TERMINATION
Precision Edge(R) SY89831U Precision Edge(R)
SY89831U
FEATURES
s Guaranteed AC performance over temperature and voltage: * DC-to > 2.0GHz throughput * <450ps propagation delay (IN-to-Q) * < 20ps within-device skew * < 225ps rise/fall time s Ultra-low jitter design: * < 1psRMS cycle-to-cycle jitter * < 1psRMS random jitter * < 10psPP deterministic jitter * < 10psPP total jitter (clock) s Unique patent-pending input termination and VT pin accepts DC- and AC-coupled differential inputs s 800mV, 100K LVPECL output swing s Power supply 2.5V 5% or 3.3V 10% s Industrial temperature range: -40C to +85C s Available in 16-pin (3mm x 3mm) MLF(R) package Precision Edge(R)
DESCRIPTION
The SY89831U is a high-speed, 2GHz differential LVPECL 1:4 fanout buffer optimized for ultra-low skew applications. Within device skew is guaranteed to be less than 20ps (5ps typ.) over supply voltage and temperature. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference output is included for AC-coupled applications. The SY89831U is a part of Micrel's high-speed clock synchronization family. For applications that require a different I/O combination, consult Micrel's website at www.micrel.com, and choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators and clock generators.
APPLICATIONS
s s s s Processor clock distribution SONET clock distribution Fibre Channel clock distribution Gigabit Ethernet clock distribution
FUNCTIONAL BLOCK DIAGRAM
1:4 Q0 /Q0
TYPICAL PERFORMANCE
155MHz Output
/Q
Q1
IN VT /IN 50 50
Output Swing (150mV/div.)
/Q1
TA = 25C VCC = 3.3V VEE GND VIN = 800mV Q
Q2 /Q2
D Q
VREF-AC EN (TTL/CMOS)
Q3
TIME (1ns/div.)
/Q3
Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc. M9999-020707 hbwhelp@micrel.com or (408) 955-1690
Rev.: D Amendment: /0
1
Issue Date: February 2007
Micrel, Inc.
Precision Edge(R) SY89831U
PACKAGE/ORDERING INFORMATION
VCC GND /Q0 Q0
Ordering Information(1)
12 11 10 9
16
15
14
13
Q1 /Q1 Q2 /Q2
1 2 3 4 5 6 7 8
IN VT VREF-AC /IN
Part Number SY89831UMI SY89831UMITR(2) SY89831UMG(3) SY89831UMGTR(2, 3)
Package Type MLF-16 MLF-16 MLF-16 MLF-16
Operating Range Industrial Industrial Industrial Industrial
Package Marking 831U 831U 831U with Pb-Free bar-line indicator 831U with Pb-Free bar-line indicator
Lead Finish Sn-Pb Sn-Pb NiPdAu Pb-Free NiPdAu Pb-Free
/Q3
Q3
VCC
EN
16-Pin MLF(R) (MLF-16)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs.
PIN DESCRIPTION
Pin Number 15, 16 1, 2, 3, 4, 5, 6 8 Pin Name Q0, /Q0 Q1, /Q1 Q2, /Q2 Q3, /Q3 EN Pin Function Differential 100K LVPECL Outputs: These LVPECL outputs are the precision, low skew copies of the inputs. Please refer to the "Truth Table" section for details. Unused output pairs may be left open. Terminate wtih 50 to VCC-2V. See "Output Termination Recommendations" section for more details. This single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The synchronous enable ensures that enable/disable will only occur when the outputs are in a logic LOW state. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state (enabled) if left open. Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-Coupled differential signs as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50. Note that these inputs will default to an intermediate state if left open. Pleae refer to the "Input Interface Applications" section for more details. Reference Voltage: These outputs bias to VCC-1.4V. They are used when AC coupling the inputs (IN, /IN). For AC-Coupled applications, connect VREF-AC to VT pin and bypass with 0.01F low ESR capacitor to VCC. See "Input Interface Applications" section for more details. Maximum sink/source current is 1.5mA. Due to the limited drive capability, each VREF-AC pin is only intended to drive its respective VT pin. Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT pins provide a center-tap to a termination network for maximum interface flexibility. See "Input Interface Applications" section for more detaiils. Ground. GND pins and exposed pad must be connected to the most negative potential of the device ground. Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors and place as close to each VCC pin as possible.
9, 12
/IN, IN
10
VREF-AC
11
VT
13 7, 14
GND VCC
TRUTH TABLE
IN 0 1 X /IN 1 0 X EN 1 1 0 Q 0 1 0(1) /Q 1 0 1(1)
Note: 1. On next negative transition of the input signal (IN). M9999-020707 hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge(R) SY89831U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) .................................. -0.5V to +4.0V Input Voltage (VIN) ............................... -0.5V to VCC +0.5V LVPECL Output Current (IOUT) Continuous ......................................................... 50mA Surge ................................................................ 100mA Input Current Source or Sink Current on (IN, /IN) .................. 50mA VREF-AC Current Source or Sink Current on (IVT) .......................... 2mA Lead Temperature (soldering, 20sec.) ...................... 260C Storage Temperature (TS) ....................... -65C to +150C
Operating Ratings(2)
Supply Voltage Range ........................ +2.375V to +2.625V ............................................................ +3.0V to +3.6V Ambient Temperature (TA) ......................... -40C to +85C Package Thermal Resistance(3) MLF(R) (JA) Still-Air ........................................................ 60C/W (JB) Junction-to-Board ...................................... 32C/W
DC ELECTRICAL CHARACTERISTICS(4)
TA = -40C to +85C, unless otherwise stated. Symbol VCC ICC RIN RDIFF-IN VIH VIL VIN VDIFF_IN VREF-AC Parameter Power Supply Power Supply Current Input Resistance (IN-to-VT) Differential Input Resistance (IN-to-/IN) Input HIGH Voltage (IN, /IN) Input LOW Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing |IN - /IN| Output Reference Voltage see Figure 1a. see Figure 1b. No load, max. VCC. 45 90 VCC-1.2 0 0.1 0.2 VCC-1.525 VCC-1.425VCC-1.325 Condition Min 2.375 3.0 47 50 100 Typ Max 2.625 3.6 70 55 110 VCC VIH-0.1 1.7 Units V mA V V V V V
LVTTL/LVCMOS INPUT DC ELECTRICAL CHARACTERISTICS
VCC = 2.375V to 3.60V; VEE = 0V; TA = -40C to +85C Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Condition Min 2.0 0 -125 -300 Typ Max VCC 0.8 20 Units V V A A
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. JB and JA values are determined for a 4-layer board in stil-air number, unless otherrwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge(R) SY89831U
LVPECL OUTPUT DC ELECTRICAL CHARACTERISTICS(6)
VCC = +2.5V 5% or +3.3V 10%; RL = 50 to VCC -2V; TA = -40C to +85C unless otherwise stated. Symbol VOH VOL VOUT VDIFF_OUT Parameter Output HIGH Voltage (Q, /Q) Output LOW Voltage (Q, /Q) Output Voltage Swing (Q, /Q) Differential Output Voltage Swing (Q, /Q) See Figure 1a. See Figure 1b. Condition Min VCC-1.145 VCC-1.945 550 1100 800 1600 Typ Max VCC-0.895 VCC-1.695 Units V V mV mV
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(6)
VCC = +2.5V 5% or +3.3V 10%; TA = -40C to +85C unless otherwise stated. Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Voltage Input LOW Voltage -125 -300 Condition Min 2.0 Typ Max VCC 0.8 30 Units V V A A
Notes: 6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
Precision Edge(R) SY89831U
AC ELECTRICAL CHARACTERISTICS(7)
VCC = +2.5V 5% or +3.3V 10%; RL = 50 to VCC -2V; TA = -40C to +85C unless otherwise stated. Symbol fMAX tpd tSKEW tS tH tJITTER Parameter Maximum Frequency Propagation Delay IN-to-Q IN-to-Q Within-Device Skew Part-to-Part Skew Set-Up Time Hold Time EN to IN, /IN EN to IN, /IN Condition VOUT 450mV VIN 100mV VIN 800mV Note 8 Note 9 Note 10 Note 10 Note 11 Note 12 Note 13 Note 14 At full output swing. 70 150 300 300 1 10 1 10 225 250 Min 2.0 Typ 2.5 390 350 5 450 20 150 Max Units GHz ps ps ps ps ps ps psRMS psPP psRMS psPP ps
Data Random Jitter (RJ) Deterministic Jitter (DJ) Clock Cycle-to-Cycle Jitter Total Jitter (TJ)
tr, tf
Notes: 7. 8. 9.
Output Rise/Fall Times (20% to 80%)
High-frequency AC parameters are guaranteed by design and characterization. Within device skew is measured between two different outputs under identical input transitions. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs.
10. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold times do not apply. 11. Random jitter is measured with a K28.7 pattern, measured at fMAX. 12. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 223-1 PRBS pattern. 13. Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn -Tn+1, where T is the time between rising edges of the output signal. 14. Total jitter definition: with an ideal clock input frequency of fMAX (device), no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value.
TIMING DIAGRAM
EN VCC/2 tS /IN IN VIN tpd /Q Q VOUT tH VCC/2
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Micrel, Inc.
Precision Edge(R) SY89831U
TYPICAL OPERATING CHARACTERISTICS
VCC = 3.3V, GND = 0V, RL = 50 to VCC-2V, TA = 25C, unless otherwise stated.
Output Swing vs. Frequency
900 PROPAGATION DELAY (ps) 800 OUTPUT SWING (mV) 700 600 500 400 300 200 100 0 0 1000 2000 FREQUENCY (MHz) 3000
390 380 370 360 350 340 330 320 310
Propagation Delay vs. Temperature
450 PROPAGATION DELAY (ps) 425 400 375 350 325 300 100
Propagation Delay vs. Input Voltage Swing
300 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
300 500 700 900 INPUT VOLTAGE SWING (V)
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
6
Micrel, Inc.
Precision Edge(R) SY89831U
FUNCTIONAL CHARACTERISTICS
VCC = 3.3V, GND = 0V, VIN = 800mV, RL = 50 to VCC-2V, TA = 25C, unless otherwise stated.
155MHz Output
622MHz Output
/Q Output Swing (150mV/div.) Output Swing (150mV/div.) Q
/Q
Q
TIME (1ns/div.)
TIME (200ps/div.)
1GHz Output
/Q Output Swing (150mV/div.) Q
TIME (150ps/div.)
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Micrel, Inc.
Precision Edge(R) SY89831U
SINGLE-ENDED AND DIFFERENTIAL SWINGS
VIN, VOUT 800mV (typical)
VDIFF_IN, VDIFF_OUT 1.6V (typical)
Figure 1a. Single-Ended Swing
Figure 1b. Differential Swing
INPUT AND OUTPUT STAGES
VCC
IN 50 VT 50 /IN
VCC
/Q
SY89831U
Q
Figure 2a. Simplified Differential
Figure 2b. Simplified LVPECL Output Stage
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
Precision Edge(R) SY89831U
INPUT INTERFACE APPLICATIONS
VCC VCC VCC IN IN
LVPECL
LVPECL
VCC VCC VCC
/IN /IN SY89831U Rpd Rpd VCC VT VREF-AC 0.01F NC NC SY89831U CML
IN /IN SY89831U VT VREF-AC
VCC
VCC - 2V 0.01F Rpd VT VREF-AC
For 2.5V, Rpd = 19 . For 3.3V, Rpd = 50 .
For 2.5V, Rpd = 50 For 3.3V, Rpd = 100
Figure 3a. DC-Coupled LVPECL Input Interface
Figure 3b. AC-Coupled LVPECL Input Interface
Figure 3c. DC-Coupled CML Input Interface
VCC
VCC
VCC
VCC
IN CML /IN SY89831U VCC VT VREF-AC 0.01F NC NC LVDS
IN /IN SY89831U VT VREF-AC
Figure 3d. AC-Coupled CML Input Interface
Figure 3e. LVDS Interface
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
Precision Edge(R) SY89831U
OUTPUT TERMINATION RECOMMENDATIONS
+3.3V +3.3V Z = 50 Z = 50 +3.3V 50 "source" ZO = 50 R2 82 R2 82 50 Vt = VCC --2V Rb 50 "destination" VCC +3.3V
+3.3V
ZO = 50
R1 130
R1 130
C1 0.01F (optional)
Figure 5. Three-Resistor "Y-Termination" Figure 4. Parallel Termination-- Thevenin Equivalent
Note: 1. For +2.5V systems: R1 = 250, R2 = 62.5. Notes: 1. Power-saving alternative to Thevenin termination. 2. Place termination resistors as close to destination inputs as possible. 3. Rb resistor sets the DC bias voltage, equal to Vt. For +2.5V systems Rb = 19. 4. C1 is an optional bypass capacitor intended to compensate for any tr/tf mismatches.
RELATED PRODUCT AND SUPPORT DOCUMENTATION
Part Number SY89830U SY89832U SY89833U SY89834U Function 1:4 LVPECL Fanout Buffer w/2:1 MUX Input 2.5V Ultra-Precision 1:4 LVDS Fanout Buffer/ Translator with Internal Termination 3.3V Ultra-Precision 1:4 LVDS Fanout Buffer/ Translator with Internal Termination Data Sheet Link www.micrel.com/product-info/products/sy89830u.shtml www.micrel.com/product-info/products/sy89832u.shtml www.micrel.com/product-info/products/sy89833u.shtml
2.5/3.3V Two Input, 1GHz LVTTL/CMOS-to-LVPECL www.micrel.com/product-info/products/sy89833u.shtml 1:4 Fanout Buffer/Translator www.micrel.com/product-info/products/solutions.shtml www.amkor.com/products/notes_papers/MLF_AppNote_0301.pdf 16-MLF(R) Manufacturing Guidelines Exposed Pad Application Note
HBW Solutions New Products and Applications
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
10
Micrel, Inc.
Precision Edge(R) SY89831U
16-PIN EPAD MicroLeadFrame(R) (MLF-16)
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 16-Pin MLF(R) Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: Note 1. Note 2. Package meets Level 2 moisture sensitivity classification, and are shipped in dry-pack form. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
USA
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. M9999-020707 hbwhelp@micrel.com or (408) 955-1690
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